The present invention relates in general to integrated circuit input/output circuits, and more particularly to a matrix arrangement for providing switched access of a plurality of signals to I/O ports.
The large scale integration of a number of devices or circuits allows numerous functions to be carried out within a single integrated circuit. On the one hand, semiconductor dies or chips can be made larger to accommodate a larger number of circuits and corresponding functions. Conversely, significant improvements in lithography techniques have been achieved in order to make the existing circuits smaller so that additional circuits can be formed within a chip, without utilizing a larger-sized semiconductor chip. In order to utilize the functions provided by the circuits formed within the chip, I/O pins or ports are necessary. In some situations, if additional I/O pins are needed, then they are simply added to the chip as a metallic pad or pin. It can be appreciated that, based on a given size of the semiconductor die, only a reasonable number of I/O pins can be accommodated. Some integrated circuits, especially those that are microprocessor-based, have more than one hundred I/O pins. The I/O pins can be formed not only on the edge of the chip, but also on the planer face of the chip.
A problem exists when there are more signals or functions than corresponding pins available to the integrated circuit. One practice has been to multiplex a few number of signals, such as two or three, with respect to a single I/O pin. The multiplexing is carried out by a simple logic circuit that selects one of the three signals to use the I/O pin at any given time. Although this limited I/O pin sharing feature provides a certain degree of flexibility, there exists other situations in which this solution is not acceptable. There are various applications in which an integrated circuit provides more functions than can be accommodated by a full pin-out integrated circuit. In such situations, it is often the case that not all functions are required at the same time. In other applications, different users require the standard integrated circuit to be packaged with fewer than the standard number of I/O pins. In both applications, the dilemma is not easily overcome.
From the foregoing, it can be seen that a need exists for a technique to improve the flexibility by which the various signals or functions of an integrated circuit device are made available to the I/O pins. Another need exists for a switch matrix that allows many different signals or functions to be applied to many different I/O pins, while yet minimizing the semiconductor area utilized.
In accordance with the principles and concepts of the invention, there is disclosed a switching matrix that allows a plurality of different signals to be applied to each of a fewer number of I/O pins of a device. In accordance with a preferred form of the invention, a logic cell is replicated to form a cross-bar switching matrix so that the various signals generated on a chip can be routed to desired I/O pins. The signals can thus be routed to the I/O pins based on assignment by a microprocessor.
The cross-bar matrix includes plural cells defining rows and columns. Each row of cells receives a common data signal from a data resources, and each column of cells is associated with a common I/O pin of the integrated circuit. Each cell of a row receives a separate enable or control signal which enables a cell to couple therethrough the data signal to the corresponding I/O pin. In the preferred form, only one cell in a row is enabled for that row. The microprocessor controls which cell of each row is to be enabled so that the various signals are coupled to the desired I/O pins. By utilizing a cross-bar matrix, any data signal can be coupled to any of the I/O pins.
In addition to coupling data signals through the cells of the matrix, an output enable signal is also coupled from the data resource to the desired driver circuit of the I/O pin. Each cell includes a logic circuit controlled by the enable signal to allow coupling through the cell to the I/O driver circuit the output enable signal. The output enable signal controls the I/O driver circuit so that the I/O pin be configured either as an input pin or as an output pin, or both.
The designs of each matrix cell is made such that bidirectional signals can be coupled therethrough. To that end, each cell includes a logic circuit responsive to the enable signal for that cell, for coupling data signals input from the I/O pin to the data resource.
A high degree of flexibility is thus available in coupling the different signals between the data resource and the I/O pins of the integrated circuit.